【摘要】：隨著衛(wèi)星技術(shù)的飛速發(fā)展，空間飛行器的數(shù)量迅速增加，衛(wèi)星通信的需求越來越大。受天線增益、平臺規(guī)模的限制以及收發(fā)信機的相對運動，通信雙方常在高動態(tài)低信噪比環(huán)境下進行通信。在高動態(tài)低信噪比環(huán)境下，傳統(tǒng)解調(diào)器無法完成同步任務(wù)解調(diào)數(shù)據(jù)，，研究高動態(tài)低信噪比環(huán)境下解調(diào)器的設(shè)計對通信雙方實現(xiàn)通信至關(guān)重要。 根據(jù)高動態(tài)低信噪比的特定環(huán)境，本文提出了粗同步加精同步的兩級載波同步方案。粗同步采用兩級調(diào)頻率逼近算法估計信號參數(shù)，估計出的頻偏及頻率變化率進行初值抵消獲得動態(tài)變小的信號。采用擴展卡爾曼濾波算法實時估計信號相偏進行精同步。符號同步算法中，通過對比模N積分算法和法羅內(nèi)插算法，采用性能優(yōu)越、實現(xiàn)簡單的模N積分算法。 本文在對各種同步算法仿真研究的基礎(chǔ)上綜合評估各種算法性能及實現(xiàn)復(fù)雜度，選擇合適算法構(gòu)建解調(diào)器系統(tǒng)，對解調(diào)器整體性能進行Matlab仿真，仿真結(jié)果證明本文設(shè)計的解調(diào)器在高動態(tài)低信噪比環(huán)境下能同步解調(diào)數(shù)據(jù)，誤碼率相比BPSK理論值有約0.5dB的性能損失。本文還實現(xiàn)了基于VHDL語言的解調(diào)器邏輯實現(xiàn)，并在硬件平臺上完成調(diào)試工作，硬件測試結(jié)果表明在硬件平臺上解調(diào)器誤碼率相比BPSK理論值有約1dB的性能損失。
[Abstract]:With the rapid development of satellite technology, the number of space vehicles is increasing rapidly, and the demand for satellite communication is increasing. Due to the antenna gain, the limitation of platform size and the relative motion of transceiver, both sides often communicate in high dynamic and low SNR environment. In the environment of high dynamic and low signal-to-noise ratio, the traditional demodulator can not complete the synchronous task demodulation data, so it is very important to study the design of demodulator in the environment of high dynamic and low signal-to-noise ratio. According to the special environment of high dynamic and low signal-to-noise ratio, a two-stage carrier synchronization scheme for coarse synchronization and refined synchronization is proposed in this paper. In rough synchronization, two-stage frequency modulation approximation algorithm is used to estimate the signal parameters, and the estimated frequency offset and frequency change rate are used to cancel the initial value to obtain the signal with dynamic reduction. The extended Kalman filter (EKF) algorithm is used to estimate the signal phase offset in real time for precise synchronization. In the symbol synchronization algorithm, a simple modular N integral algorithm is implemented by comparing the modular N integral algorithm with the Farrow interpolation algorithm. Based on the simulation of various synchronization algorithms, this paper comprehensively evaluates the performance and implementation complexity of various algorithms, selects the appropriate algorithm to construct the demodulator system, and simulates the overall performance of the demodulator by Matlab. The simulation results show that the demodulator designed in this paper can synchronize the demodulation data in high dynamic and low SNR environment, and the bit error rate (BER) is about the loss of 0.5dB compared with the theoretical value of BPSK. This paper also implements the logic implementation of demodulator based on VHDL language, and accomplishes the debugging work on hardware platform. The hardware test results show that the demodulator bit error rate on the hardware platform is about the loss of 1dB compared with the theoretical value of BPSK.
【學(xué)位授予單位】：北京理工大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN763

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